Effective Method for Implementation of Wallace Tree Multiplier Using Fast Adders

Arithmetic and Logic Unit (ALU), core unit of a processor, when used for scientific computations, will spend more time in multiplications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reducing delay in the multiplier reduces the overall computation time. Wallace multipliers perform in parallel, resulting in high speed. It uses full adders and half adders in their reduction phase. Reduced Complexity Wallace multiplier will have fewer adders than normal Wallace multiplier. A new 16 [email protected] 16 multiplier is proposed with fast adders at the final stage of Wallace multipliers to reduce the delay. The presence of larger carry propagating adder indicates wallace multiplier as faster multiplier. The fast adder (Modified carry save adder) is used at the final stage of the Wallace multipliers to reduce the delay. This paper presents a detailed analysis of several fast adder architectures for high performance VLSI design. Keywords---Parallel Prefix Adder, Carry Save Adder, Wallace Multiplier, Modified Carry Save Adder, High Speed Adder. INTRODUCTION The Multiplier is one of the key hardware blocks in most of the digital and high performance systems such as digital signal processors and microprocessors. The Wallace Tree basically multiplies two unsigned integers. The conventional Wallace Tree multiplier architecture comprises of an AND array for computing the partial products, a Carry Save Adder for adding the partial products so obtained and a carry propagate adder in the final stage of addition. Design of high speed data path logic systems are one of the most substantial research area in VLSI system design. High speed addition and multiplication has always been a fundamental requirement of high performance processors and systems. The major speed limitation in any adder is in the production of carries and many authors have considered the addition problem. The basic idea of the proposed work is using n-bit binary to excess 1 code converters (BEC) to improve the speed of addition. This logic can be implemented with any type of adder to further improve the speed. The proposed 16, 32 and 64-bit adders are compared in this paper with the conventional fast adders such as carry save Journal of Innovative Research and Solutions (JIRAS) Print – ISSN:232